The fragility of the microelectronics supply chain was on display during the pandemic. While efforts have focused on increased domestic development, it will take time and major financial investment to bring new fabrication plants online. International partners, like Fraunhofer Institute for Photonic Microsystems (IPMS), are helping companies small and large access the latest research results and technologies on 200 and 300 mm silicon wafers, and the institute can help ease the financial burden of developing from scratch.
The institute’s development and support of micro-electromechanical systems (MEMS) is focused on the entire supply chain from individual processes to technology modules to complete systems, as well as process and technology support for equipment in the cleanroom. After development, Fraunhofer IPMS offers pilot production and supports technology transfer.
In the field of sensors and actuators, the institute develops, for example, capacitive ultrasonic sensors, which are offered as a platform for rapid customer-specific adaptations, providing small and medium-sized companies with cost effective access to technology.
Fraunhofer IPMS also offers evaluation kits for a cost-effective method to test application developments. With these ready-to-use setups, customers can, for example, immediately integrate the microscanner technology into their product development, since the appropriate control electronics, according to the specifications, are already included in the scope of delivery, reducing costly in-house development.
Nanoelectronic capabilities: process and product development
At the Center Nanoelectronic Technologies (CNT), Fraunhofer IPMS conducts applied research on 300 mm wafers for chip manufacturers, suppliers, equipment manufacturers and R&D partners.
A wide range of technology development and support services are offered for ultra-large-scale integration (ULSI). These include individual process developments in the areas of atomic layer deposition, chemical-mechanical polishing, wafer metallization, wafer cleaning, metrology and nanopatterning.
The CNT's cleanroom is also used to evaluate and optimize chemicals and consumables for the latest complementary metal-oxide semiconductor (CMOS) technologies and to qualify equipment. Fraunhofer IPMS says the main focus of R&D activities is in the front-end area with a focus on the integration of functionalities in wiring layers (the back end of line (BEoL) module). This mainly includes various non-volatile memories, capacitors or varactors. Together with Fraunhofer IZM-ASSID (All Silicon System Integration Center Dresden) and its focus on heterointegration and wafer level packaging, competencies are bundled in the center CEASAX (Center for Advanced CMOS & Heterointegration Saxony) and research is focused on neuromorphic computing, cryo- and quantum technology, as well as advanced packaging.
To expand the possibilities, a technology center for semiconductor metrology and process analysis was founded with the company Applied Materials, who helped install its eBeam metrology equipment at Fraunhofer IPMS. Precise metrology is crucial for quality control in the production of microchips to validate physical and electrical properties and to ensure the targeted yield.
Sustainable information and communication technology
The institute is also focused on environmental protection and sustainable practices. While the intelligent control of devices saves energy, the continuing proliferation of these devices increases energy consumption. Fraunhofer IPMS says microelectronics therefore will need new approaches to minimize the environmental impact in both manufacturing and design. The institute is working closely with Research Fab Microelectronics Germany (FMD) in the Green ICT (information and communication technology) competence center to actively promote the reduction of resource consumption. This includes energy-efficient sensor edge cloud systems (battery-free sensors and neuromorphic AI accelerators) and communication devices, such as Li-Fi and Ethernet time-sensitive networking (TSN), as well as resource-optimized electronics production on 200 mm and 300 mm wafers. The latter includes the optimization of material consumption and the substitution of critical materials in wet processes and lithography, as well as optimization of energy consumption and emissions impact.